Test embedding with discrete logarithms

Author

Lempel, Mody ; Gupta, Sandeep K. ; Breuer, Melvin A.

Author_Institution

Dept. of Comput. Sci., Univ. of Southern California, Los Angeles, CA, USA

fYear

1994

fDate

25-28 Apr 1994

Firstpage

74

Lastpage

80

Abstract

When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. In this paper the authors show how to select a feedback polynomial and an initial state (seed) for the LFSR so that all the faults of interest are detected by a minimum length test sequence. Minimality is per polynomial. The algorithm is based on finding the location of test patterns in the sequence generated by an LFSR with a specific feedback polynomial. This is based on the theory of discrete logarithms. The authors then select the shortest subsequence that includes test patterns for all the faults of interest, hence 100% fault coverage

Keywords

VLSI; automatic testing; built-in self test; fault location; integrated circuit testing; logic testing; sequential circuits; shift registers; VLSI circuits; built-in self test; discrete logarithms; fault coverage; feedback polynomial; initial state; linear feedback shift register; minimum length test sequence; test embedding; test patterns; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Linear feedback shift registers; Polynomials; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Conference_Location

Cherry Hill, NJ

Print_ISBN

0-8186-5440-6

Type

conf

DOI

10.1109/VTEST.1994.292331

Filename

292331