• DocumentCode
    1872193
  • Title

    Design Optimization of a 35nm Independently-Double-Gated Flexfet SOI Transistor

  • Author

    Chintala, R.S. ; Vootkuri, S. ; Parke, S.A.

  • Author_Institution
    Tennessee Tech. Univ., Cookeville
  • fYear
    2007
  • fDate
    1-4 Oct. 2007
  • Firstpage
    67
  • Lastpage
    68
  • Abstract
    Flexfet is a new SOI IDG-CMOS technology with a damascene metal top gate and an implanted JFET bottom gate that are self-aligned in a gate trench. The independent top and bottom gates are contacted at opposite sides of the channel by a local interconnect that is embedded in the isolation region between devices. A simple analytical dynamic threshold voltage model is developed and verified by extensive device simulation. Optimization of the topgate oxide thickness, silicon thickness, and gate work functions for a 35 nm long NMOSFET is achieved by device simulation. Ideal 1.0V/V dynamic threshold control of this device is achieved.
  • Keywords
    CMOS integrated circuits; MOSFET; junction gate field effect transistors; nanoelectronics; optimisation; semiconductor device models; silicon-on-insulator; NMOSFET; SOI IDG-CMOS technology; analytical dynamic threshold voltage model; damascene metal top gate; device dynamic threshold control; extensive device simulation; gate trench; implanted JFET bottom gate; independently-double-gated Flexfet SOI transistor; optimization; silicon thickness; size 35 nm; topgate oxide thickness; Analytical models; Conference proceedings; Design optimization; Isolation technology; MOSFET circuits; Semiconductor device modeling; Silicon; Thickness control; Threshold voltage; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2007 IEEE International
  • Conference_Location
    Indian Wells, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-0879-5
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2007.4357855
  • Filename
    4357855