Title :
Fault-tolerant VLSI processor array for the SVD
Author :
Cavallaro, Joseph R. ; Near, Christopher D. ; Uyar, M. Ümit
Author_Institution :
Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Abstract :
Dynamic reconfiguration techniques are presented for a two-dimensional systolic array for the singular value decomposition (SVD) of a matrix. Extra computation time is not required, since idle time inherent in the array is exploited. This scheme does not require additional spare processors and is easily implemented in VLSI. Only minor hardware and communication time increases within each processing element are required
Keywords :
VLSI; cellular arrays; fault tolerant computing; dynamic reconfiguration; fault tolerant VLSI processor array; matrix; singular value decomposition; two-dimensional systolic array; Array signal processing; Concurrent computing; Fault tolerance; Hardware; Image processing; Matrix decomposition; Signal processing algorithms; Singular value decomposition; Systolic arrays; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63351
