Title :
A design-for-test technique for switched-capacitor filters
Author :
Soma, Mani ; Kolarik, Vladimir
Author_Institution :
Washington Univ., Seattle, WA, USA
Abstract :
The paper describes a design-for-test technique for switched-capacitor (SC) filters to improve controllability and observability of internal nodes. Timing strategies employing existing clock phases in SC circuits are used to sensitize signal propagating paths, thus enhancing the circuit testability. The overhead in terms of extra control logic is small (several simple gates). Since there are no extraneous devices inserted in the analog signal path, there is no performance penalty in the normal operation of the filters
Keywords :
design for testability; integrated circuit testing; linear integrated circuits; mixed analogue-digital integrated circuits; switched capacitor filters; IC design; IC test; SC circuits; circuit testability; clock phases; control logic; controllability; design-for-test technique; internal nodes; observability; switched-capacitor filters; timing strategies; Circuit faults; Circuit testing; Clocks; Design for testability; Filters; Observability; Signal generators; Switches; System testing; Timing;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292336
