Retiming sequential circuits to enhance testability

This paper presents a technique to enhance the testability of sequential circuits by repositioning registers. A novel retiming for testability technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundancies, and yields retimed circuits that usually require fewer scan registers to break all cycles (except self-loops) as compared to the original circuit. The retiming technique is based on a new minimum cost flow formulation that simultaneously considers the interactions among all strongly connected components (SCCs) of the circuit to minimize the number of registers in the SCCs. Experimental results on several large sequential circuits demonstrate the effectiveness of the proposed retiming for testability technique