65nm CMOS BULK to SOI comparison

Author

Pelloie, J.L. ; Laplanche, Y. ; Chen, T.F. ; Huang, Y.T. ; Liu, P.W. ; Chiang, W.T. ; Huang, M.Y.T. ; Tsai, C.H. ; Cheng, Y.C. ; Tsai, C.T. ; Ma, G.H.

Author_Institution

ARM, Grenoble

fYear

2007

fDate

1-4 Oct. 2007

Firstpage

79

Lastpage

80

Abstract

SOI is today mainly used for high-speed CPU applications. The advantages brought by SOI are still questioned or not clearly understood and little information has been published about the comparison between bulk and SOI CMOS. First reason is that this comparison to be representative must be done for same process features such as gate length and gate oxide thickness, second reason is that designing the same circuit in both bulk and SOI requires a significant investment. 65nm CMOS bulk and SOI both developed at UMC 12" facility with same process features are compared in this paper.

Keywords

CMOS integrated circuits; nanoelectronics; silicon-on-insulator; CMOS bulk devices; SOI; gate length; gate oxide thickness; silicon-on-insulator; size 65 nm; CMOS logic circuits; Circuit simulation; Circuit synthesis; Delay; Frequency; Implants; Integrated circuit interconnections; Semiconductor films; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2007 IEEE International

Conference_Location

Indian Wells, CA

ISSN

1078-621X

Print_ISBN

978-1-4244-0879-5

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2007.4357861

Filename

4357861