Thermal Modeling and Device Noise Properties of 3D-SOI Technology

Author

Chen, Tze Wee ; Chun, Jung Hoon ; Lu, Yi-Chang ; Navid, Reza ; Wang, Wei ; Dutton, Robert W.

Author_Institution

Stanford Univ., Stanford

fYear

2007

fDate

1-4 Oct. 2007

Firstpage

89

Lastpage

90

Abstract

This article deals with performance of 3D-IC which is influenced by thermal effects as well as 3D packaging and parasitic effects. Actual circuit performance is difficult to predict as thermal and 3D packaging effects act in opposite ways. To provide design insight, a stacked wafer 3D-SOI technology was characterized and a thermal model was developed. Electro-thermal simulations of 3D-ICs were performed, and simulation results match measured data. Device noise is measured for this technology.

Keywords

integrated circuit modelling; integrated circuit noise; semiconductor device noise; silicon-on-insulator; thermal management (packaging); wafer level packaging; 3D-SOI packaging; device noise properties; electro-thermal simulation; stacked wafer; thermal modeling; Electrical resistance measurement; Electronic packaging thermal management; Frequency; MOSFETs; Noise measurement; Oscillators; Phase noise; Temperature; Thermal degradation; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2007 IEEE International

Conference_Location

Indian Wells, CA

ISSN

1078-621X

Print_ISBN

978-1-4244-0879-5

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2007.4357866

Filename

4357866