• DocumentCode
    1872615
  • Title

    Innovative Approach to drive Floating Body Z-RAM® Embedded Memory to 32 nm and beyond

  • Author

    Fisch, David

  • Author_Institution
    Innovative Silicon, Lausanne
  • fYear
    2007
  • fDate
    1-4 Oct. 2007
  • Firstpage
    101
  • Lastpage
    102
  • Abstract
    With each new technology node the challenges of building a robust, scalable embedded memory grow. This trend drives higher process complexity and cost as well as increased capital equipment investments to support the process. In this study, the zero capacitor RAM (Z-RAM) [A SOI Capacitor-less IT-DRAM Concept, Okhonin, Nagoga, Sallese, Fazan, 2001 IEEE International SOI Conference, pp.153-154.] scalability path to 32 nm and beyond is compared to other embedded solutions. Z-RAM memory cell features and memory architecture are considered in this analysis.
  • Keywords
    integrated memory circuits; nanoelectronics; random-access storage; capital equipment investments; floating body Z-RAMreg embedded memory; size 32 nm; zero capacitor RAM; Capacitance; Circuits; Conference proceedings; High K dielectric materials; High-K gate dielectrics; Logic; MIM capacitors; Random access memory; Scalability; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2007 IEEE International
  • Conference_Location
    Indian Wells, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-0879-5
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2007.4357872
  • Filename
    4357872