Abstract :
With each new technology node the challenges of building a robust, scalable embedded memory grow. This trend drives higher process complexity and cost as well as increased capital equipment investments to support the process. In this study, the zero capacitor RAM (Z-RAM) [A SOI Capacitor-less IT-DRAM Concept, Okhonin, Nagoga, Sallese, Fazan, 2001 IEEE International SOI Conference, pp.153-154.] scalability path to 32 nm and beyond is compared to other embedded solutions. Z-RAM memory cell features and memory architecture are considered in this analysis.
Keywords :
integrated memory circuits; nanoelectronics; random-access storage; capital equipment investments; floating body Z-RAMreg embedded memory; size 32 nm; zero capacitor RAM; Capacitance; Circuits; Conference proceedings; High K dielectric materials; High-K gate dielectrics; Logic; MIM capacitors; Random access memory; Scalability; Silicon;
