The effects of thermal processing on CMOS device performance

As CMOS scaling continues its rapid pace process development runs into ever greater challenges. To meet gate length requirements, sharper, shallower source/drain junctions are necessary. They must be highly doped and activated to minimize resistance of the carriers as they travel from the channel to the contact. Contact resistance must be as low as possible to minimize IR drops. Active concentration of dopant in the poly gate must be maximized in order to reduce poly depletion, but not at the expense of allowing dopant from the poly to diffuse through the gate oxide and counter-dope the channel. These are just a few of the tasks facing process development and integration. This paper looks at the problems using simulation. An idealized transistor is used and profiles in source, drain, channel and poly are varied to determine key factors that limit device performance.