Millimeter wave design with 65 nm LP SOI HR CMOS technology

In this paper, we present active and passive performances of the 65 nm LP SOI HR technology from STMicroelectronics and two simulated circuits to illustrate the potentiality of the technology for millimeter wave (mm-wave) applications. 65 nm low power (LP) partially depleted (PD) n-MOSFET floating body (FB) shows a f/f_max of 160/200 GHz. Coplanar waveguides (CPW) present a measured attenuation constant lower than 1 dB/mm at 60 GHz for 45 Omega and 70 Omega characteristic impedance (Zc). The 60 GHz simulated Low Noise Amplifier (LNA) shows 22 dB gain, an input/output reflection losses <-14 dB and a noise figure (NF) of 5.5 dB while dissipating 72 m W under a 2.4 V supply. The resistive drain pumped mixer shows 7.7 dB conversion losses, a NF of 12 dB for a P_LO=-5 dBm (local oscillator power). This architecture shows a simulated linearity performance IP_{1 dB} of - 10 dBm and an IIP₃ of 0 dBm with muW power consumption.