Title :
Ultra thin oxide characterization with MBE deposited poly silicon
Author :
Stadler, A. ; Schulze, J. ; Tolksdorf, C. ; Sedimaier, S. ; Eisele, I. ; Dietl, W. ; Roters, G.L. ; Nényei, Z.
Author_Institution :
Inst. fur Phys., Univ. der Bundeswehr Munchen, Neubiberg, Germany
Abstract :
In this paper we present a new approach to determine Dit and QBD of the Si-SiO2 interface by using a highly doped Poly-Si electrode deposited by molecular beam epitaxy (MBE) where no Hydrogen is present in the depositing ambient. This allows the optimization of the inherent surface state density of different gate dielectrics without unintentional H-annealing and in addition combines the advantages of the standard techniques for Dit determination: the commercially available techniques, e.g. QuantoxTM, and the conventional Poly-Si electrode method were the Poly-Si is deposited by means of chemical vapour deposition (CVD). It appears that one can direct compare the Dit of the presented approach with the Dit measured with surface photo voltage (SPV) by QuantoxTM. On the other hand the conventional CVD Poly-Si electrode measurements can be simulated by subsequent annealing of the MBE Poly-Si electrode in a controlled H-ambient introducing Hydrogen to the interface. Therefore the gap between the commercially available measurements and the conventional Poly-Si method is closed and therefore a deeper understanding of the "real" interface state density and the break down behaviour even under "production condition" can be obtained.
Keywords :
electric breakdown; elemental semiconductors; molecular beam epitaxial growth; semiconductor epitaxial layers; semiconductor-insulator boundaries; silicon; silicon compounds; surface states; Si-SiO2; Si-SiO2 interface; charge-to-breakdown; gate dielectric; interface state density; molecular beam epitaxy; polysilicon electrode; surface state density; ultrathin oxide; Chemical vapor deposition; Density measurement; Dielectrics; Electrodes; Hydrogen; Interface states; Molecular beam epitaxial growth; Silicon; Simulated annealing; Voltage;
Conference_Titel :
Advanced Thermal Processing of Semiconductors 9th Internationa Conference on RTP 2001
Print_ISBN :
0-9638251-0-4
DOI :
10.1109/RTP.2001.1013754