DocumentCode :
1873140
Title :
Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultra-Thin Body nMOSFETs with SOI Thickness of Less Than 2 nm
Author :
Shimizu, Ken ; Hiramoto, Toshiro
Author_Institution :
Tokyo Univ., Tokyo
fYear :
2007
fDate :
1-4 Oct. 2007
Firstpage :
145
Lastpage :
146
Abstract :
Much attention has been paid to ultra-thin body (UTB) and double-gate (DG) MOSFETs because of their superior immunity to short channel effect. However, it has been reported that the electron mobility is degraded in DG compared with single-gate (SG) in (100) UTB nMOSFETs with SOI thickness (tSOI) of around 5-15 nm (Uchida et al., 2003). On the other hand, it has been reported that the hole mobility is enhanced in (100) DG pMOSFETs with tSOI of around 5-6 nm (Tsutsui et al., 2006). In order to design nano-scale DG CMOSFETs such as FinFETs, it is quite important to understand electron mobility behaviors in DG and to identify the suitable device parameters without mobility degradation. In this study, electron mobility in (100) SG and DG with tSOI of less than 5 nm is experimentally investigated. It is found for the first time that no mobility degradation in DG compared with SG occurs when tSOI is 1.7 nm due to strong quantum confinement by ultimately thin SOI.
Keywords :
MOSFET; electron mobility; nanotechnology; silicon-on-insulator; FinFET; SOI thickness; double-gate ultrathin body nMOSFET; electron mobility degradation; nanoscale DG CMOSFETs; Capacitive sensors; Conference proceedings; Degradation; Electron mobility; Electrostatics; Immune system; MOSFETs; Particle scattering; Phonons; Shape;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2007 IEEE International
Conference_Location :
Indian Wells, CA
ISSN :
1078-621X
Print_ISBN :
978-1-4244-0879-5
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2007.4357894
Filename :
4357894
Link To Document :
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