Flexible A/D converter architecture targeting sparse signals

In this article, we examine different architectures of analog-to-digital converters (ADCs) and propose a flexible architecture based on sampling by crossing levels and adaptive quantization step, aiming at reducing the energy required to convert and process specific signals. The proposed architecture has parameters which can be configured by the user, in order to adapt the conversion process to the signal being sampled and to the requirements of power consumption of the target application. The architecture was modeled and simulated using Matlab, and tested with different signals, including an Electrocardiogram (ECG) signal. The digital logic was implemented in FPGA from a SystemVerilog description, functionally compatible with the Matlab model, and the analog part was implemented with discrete components.