Optimal phase changing frequency determination for multiphase voltage regulator modules

Modern processers have the capability of indicating the power state of the processor to the Voltage Regulator (VR) PWM controller so that it can change its operating state to maximize efficiency at light loads and to flatten out its efficiency curve for idle power reduction. The CPU worst case assert and de-assert frequency can be very high for the PWM controller and for the VR to follow. Thus for the VR to take advantage of the low power state signal from the CPU, the signal has to be passed through an analog/digital low-pass filter. The optimum frequency for this filter design is determined in this paper. This filtered frequency with which the VR drops its phases optimizes the overall efficiency of the system. The experimental results are given for a four-phase VRM. It is also shown in this paper that the transient efficiency is as vital as the steady state efficiency considering the load profile of modern CPUs.