Design and Efficient FPGA Implementation of Ghash Core for AES-GCM

AES-GCM(Advanced Encryption Standard with Galois Counter Mode) is an encryption authentication algorithm, which includes two main components: an AES engine and Ghash module. Because of the computation feedback in Ghash operation, the Ghash module limits the performance of the whole AES-GCM system. In this study, an efficient architecture of Ghash is presented. The architecture uses an optimized bit-parallel multiplier. In addition, based on this multiplier, pipelined method is adopted to achieve higher clock rate and throughput. We also introduce a redundant register method, which is never mentioned before, for solving the big fan- out problem derived from the bit-parallel multiplier. In the end, the performance of proposed design is evaluated on Xilinx virtex4 FPGA platform. The experimental results show that our Ghash core has less clock delay and can easily achieve higher throughput, which is up to 40Gbps.