DocumentCode
1874040
Title
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines
Author
Takahashi, Hiroshi ; Higami, Yoshinobu ; Kikkawa, Toru ; Aikyo, Takashi ; Takamatsu, Yuzo ; Yamazaki, Koji ; Tsutsumi, Toshiyuki ; Yotsuyanagi, Hiroyuki ; Hashizume, Masaki
Author_Institution
Ehime Univ., Matsuyama
fYear
2007
fDate
26-28 Sept. 2007
Firstpage
243
Lastpage
251
Abstract
In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with don´t cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that (1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and (2) the proposed method is able to reduce the number of indistinguished open fault pairs.
Keywords
circuit reliability; circuit testing; fault diagnosis; DSM circuits; adjacent lines; diagnostic test generation; open faults; stuck-at fault test; test generation; Benchmark testing; Circuit faults; Circuit testing; Fault detection; Fault diagnosis; Fault tolerant systems; Integrated circuit interconnections; System testing; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on
Conference_Location
Rome
ISSN
1550-5774
Print_ISBN
978-0-7695-2885-4
Type
conf
DOI
10.1109/DFT.2007.11
Filename
4358393
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