Title :
A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme
Author_Institution :
STMicroelectronics Ltd, Noida
Abstract :
Newer technologies like 90 nm and 65 nm bring with them new challenges: longer time to process maturity, higher defect densities and poorer yields. The quality of test and repair determines the design´s final yield and profitability. With increasing amount of memory on the chip, the need for an efficient and fast converging perfect algorithm for memory repair is increasing becoming important. In this paper, a perfect algorithm is presented for standalone repairable memories as well as for situations where redundancy is shared between different memories. The proposed BISR is composed of Built-in self-test (BIST) and built-in redundancy analysis (BIRA) module. The BISR module has a low overhead - about 5.05 % of memories area for a typical automotive chip. The proper redundancy scheme and the proposed BIRA algorithm ensure a high repair rate for the SOC and shorter test times as well as optimized area and maximum performance.
Keywords :
built-in self test; semiconductor storage; system-on-chip; 2D redundancy scheme; BISR; SOC; built in redundancy analysis; built in self test; perfect algorithm; semiconductor memories; sharable built in self-repair; size 65 nm; size 90 nm; standalone repairable memories; Approximation algorithms; Built-in self-test; Heuristic algorithms; History; Logic design; Random access memory; Redundancy; Semiconductor memory; Silicon; Testing;
Conference_Titel :
Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on
Conference_Location :
Rome
Print_ISBN :
978-0-7695-2885-4
DOI :
10.1109/DFT.2007.28
