DocumentCode
1874597
Title
Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits
Author
Neophytou, Stelios ; Michael, Maria K.
Author_Institution
Univ. of Cyprus, Nicosia
fYear
2007
fDate
26-28 Sept. 2007
Firstpage
439
Lastpage
447
Abstract
Identification of bits that do not necessarily have to be specified in a test set can be beneficial to a number of applications, including low power test, test set encoding and embedding, and test set enriching with n-detect or other fault types properties. This work presents a new method for generating tests containing only a small number of specified bits, while keeping the number of total tests small. The method relies on finding a large number of faults that can be detected by a single test (compatible faults) with a small number of specified bits. Both the total number of specified bits in the test set as well as the number of specified bits per test are minimized. The obtained experimental results show that the proposed methodology can generate compact test sets with an average of 60% of unspecified bits, outperforming existing methods that consider this problem.
Keywords
VLSI; automatic test pattern generation; integrated circuit testing; hierarchical fault compatibility identification; low power test; test generation; test set embedding; test set encoding; test set enriching; Automatic test pattern generation; Compaction; Distributed power generation; Encoding; Fault detection; Fault diagnosis; Fault tolerant systems; Power generation; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on
Conference_Location
Rome
ISSN
1550-5774
Print_ISBN
978-0-7695-2885-4
Type
conf
DOI
10.1109/DFT.2007.46
Filename
4358413
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