Title :
Access To Vectors In Multi-module Memories
Author :
Valero, Mateo ; Peiron, Montse ; Ayguadé, Eduard
Author_Institution :
Departarnent d´´Arquitectura de Computadors, Universitat Politecnica de Catalunya, Spain
Keywords :
Bandwidth; Cache memory; Computer networks; Degradation; Delay; Intelligent networks; Interleaved codes; Memory management; Multiprocessing systems; Multiprocessor interconnection networks;
Conference_Titel :
Parallel and Distributed Processing, 1994. Proceedings. Second Euromicro Workshop on
Print_ISBN :
0-8186-5370-1
DOI :
10.1109/EMPDP.1994.592494