Clock distribution in high speed systems

Several industry trends, such as increasing clock frequencies, tighter timing control requirements and more synchronous loads, have lead to a concern on the part of system designers over clock signal quality and clock distribution. This is a valid concern because current technology has resulted in more complex and sensitive designs as well as fast output edge rates. Many issues that could safely be ignored in the past have now been brought to the foreground. The old argument for synchronous interfaces is winning in many areas and more and more clock loads are popping up on boards. When tied in with the perpetual quest to maintain or gain performance, these factors clearly show why much attention has in the last year or two been focused on clock drivers and clock distribution. This paper discusses some of the key issues pertaining to clock signal integrity and reliability, meeting stringent timing requirements and selection of a suitable clock driver for one´s given application