• DocumentCode
    1875742
  • Title

    Issues of advanced architectural features in the design of a timing tool

  • Author

    Rhee, Byung-Do ; Min, Sang Lyul ; Lim, Sung-Soo ; Shin, Heonshik ; Kim, Chong Sang ; Park, Chang Yun

  • Author_Institution
    Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
  • fYear
    1994
  • fDate
    18-19 May 1994
  • Firstpage
    59
  • Lastpage
    62
  • Abstract
    This paper describes a timing tool being developed by a real-time research group at Seoul National University. Our focus is on the issues resulting from advanced architectural features such as pipelined execution and cache memories found in many modern RISC-style processors. For each architectural feature we state the issues and explain our approach
  • Keywords
    buffer storage; computational complexity; parallel architectures; performance evaluation; pipeline processing; real-time systems; reduced instruction set computing; RISC-style processors; architectural features; cache memories; pipelined execution; real-time computing systems; real-time research; timing tool; Assembly; Cache memory; Contracts; Information analysis; Microprocessors; Pipeline processing; Processor scheduling; Program processors; Real time systems; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real-Time Operating Systems and Software, 1994. RTOSS '94, Proceedings., 11th IEEE Workshop on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    0-8186-5710-3
  • Type

    conf

  • DOI
    10.1109/RTOSS.1994.292560
  • Filename
    292560
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1875742