Switching loss analysis considering parasitic loop inductance with current source drivers for buck converters

In this paper, the switching loop inductance was investigated on the Current Source Drivers (CSDs). The analytical model was developed to predict the switching losses. It is noted that although the CSDs can reduce the switching transition time and switching loss greatly, the switching loop inductance still has the current holding effect on the CSDs. This results in high turn off loss for the control MOSFET in a buck converter. Thus, an improved layout was proposed to achieve minimum switching loop inductance. The experimental results verified the significant switching loss reduction owing to the proposed layout of a buck converter with 12 V input, 1.3 output and 1MHz.