Implementation of Sigma-Delta Analog to Digital Converter in FPGA

This paper presents implementation of a second-order Sigma-Delta Analog to Digital Converter (ADC) for audio band in field-programmable gate array (FPGA) Xilinx Virtex5. This family of FPGA contains a differential input buffers, which are used to create a continuous-time integrators as a loop filter stages. The implementation is done using hardware description language (VHDL).