Different strokes: how to cascade and parallel FIFOs of various architectures

FIFOs are memory components internally. But they interact with the system of which they are part, and with each other, like logic devices. FIFOs often are used in arrays, to expand the memory available within the ´effective FIFO´ which is required by the system. The expansion may be either in depth (the number of memory words), or in width (the number of bits within one memory word), or in both depth and width at once. Recent FIFOs include architectural features to make depth expansion (cascading) and width expansion (paralleling) both more designer-friendly and more reliable. Four different cascading architectures are in widespread use today. Architectural support for paralleling comes down simply to providing extra ´enable´ control inputs