Title :
New features in synchronous FIFOs
Author_Institution :
Paradigm Technol. Inc., San Jose, CA, USA
Abstract :
FIFOs are key components in high speed system design. They buffer data at high speed without waiting and solve clock skew problems. Synchronous FIFOs introduce a new architecture which combines higher performance for a given technology coupled with ease of interface and better timing margins than previous architectures. For these reasons, synchronous FIFOs are replacing asynchronous FIFOs in most applications
Keywords :
buffer storage; integrated memory circuits; memory architecture; timing; architecture; clock skew elimination; clocked interfaces; data buffer; high speed system design; synchronous FIFOs; timing margins; Clocks; Control systems; Cost function; Counting circuits; Damping; Data buses; Logic arrays; Read-write memory; Resistors; Timing;
Conference_Titel :
Northcon/93. Conference Record
Conference_Location :
Portland, OR
Print_ISBN :
0-7803-9972-2
DOI :
10.1109/NORTHC.1993.505059
