DocumentCode
187704
Title
65 nm fault tolerant latch architecture based on transient propagation blocking
Author
Glorieux, M. ; Clerc, Sylvain ; Gasiot, Gilles ; Autran, Jean-Luc ; Roche, Philippe
Author_Institution
STMicroelectron., Crolles, France
fYear
2014
fDate
1-5 June 2014
Abstract
A new solution is proposed to protect sequential logic against single event effects. This hardening mechanism blocks the propagation of voltage transient generated by ionizing particles and limits delay penalties as only one transistor is added in the data path. A flip-flop has been designed with this new latch in 65 nm technology and accelerated protons tests show 4× reduction of the soft-error-rate.
Keywords
fault tolerance; flip-flops; life testing; logic design; radiation hardening (electronics); sequential circuits; transients; transistor circuits; accelerated protons tests; data path; delay penalties; fault tolerant latch architecture; flip-flop; hardening mechanism; ionizing particles; sequential logic; single event effects; size 65 nm; soft-error-rate; transient propagation blocking; voltage transient; Computational modeling; Latches; MOSFET; Manganese; Neutrons; Single event upsets;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2014 IEEE International
Conference_Location
Waikoloa, HI
Type
conf
DOI
10.1109/IRPS.2014.6861173
Filename
6861173
Link To Document