DocumentCode :
187717
Title :
BTI recovery in 22nm tri-gate technology
Author :
Ramey, S. ; Hicks, J. ; Liyanage, L.S. ; Novak, Steven
Author_Institution :
Logic Technol. Dev. Quality & Reliability, Intel Corp., Hillsboro, OR, USA
fYear :
2014
fDate :
1-5 June 2014
Abstract :
BTI recovery in tri-gate devices matches data and model predictions from planar devices, indicating a consistent physical basis for the mechanism and no influence from transistor architecture features such as crystal orientation, confinement, and vertical sidewalls. This consistency enables extending existing models established on planar devices to capture temperature and voltage dependencies of recovery. A new experimental technique allows extraction of an effective activation energy for recovery. The observation of complete recovery demonstrates that no permanent damage occurs during stress.
Keywords :
MOSFET; negative bias temperature instability; semiconductor device reliability; BTI recovery; NMOS PBTI; PMOS NBTI degradation; confinement; crystal orientation; effective activation energy extraction; model predictions; planar devices; size 22 nm; transistor architecture features; tri-gate devices; tri-gate technology; vertical sidewalls; voltage dependency; Current measurement; Degradation; Logic gates; Mathematical model; Stress; Stress measurement; Temperature dependence;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium, 2014 IEEE International
Conference_Location :
Waikoloa, HI
Type :
conf
DOI :
10.1109/IRPS.2014.6861180
Filename :
6861180
Link To Document :
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