Gate bias temperature stress-induced off-state leakage in nMOSFETs: Mechanism, lifetime model and circuit design consideration

In this work, gate bias-temperature-stress (VG-BTS) induced off-state leakage current (I_off) has been comprehensively studied. During long-term operation in word-line driver of flash memory, the STI SiN-liner trapped charge which lowered the threshold voltage of STI-edge parasitic MOSFETs lead to off-state leakage or so-called word-line leakage. Both unipolar and bipolar AC stresses are performed for the phenomenon of relaxation and recovery. The H₂ diffusion (E_a=0.6eV) is major cause of interface trapping between STI oxide and nitride and also attributes to the leakage. By long-term stress results, it is shown that the dependence of lifetime and gate voltage can be described by power law V-model. Moreover, we provide the design solutions to eliminate this unexpected leakage for the reliable memory production in the future.