High dose dopant implantation to heated Si substrate without amorphous layer formation

Enhancement of transistor drivability with suppressing short channel effect is a mandatory requirement for device scaling. In order to address the requirement, transistor structure transition from 2D bulk planar to SOI or 3D FinFET structures is now proceeding[1-3]. In FinFET structures, high dose tilt implantations are used in source drain extension formation. This implantations cause amorphization of Si fins, and there exists an issue here for difficulty in regrowth of amorphized Si fins during successive activation annealing. For further scaling, fin width becomes narrower, and regrowth from crystal channel also cannot be much expected. Amorphized Si fin cannot be easily regrown to Si fin top during activation annealing, resulting in twin formation and/or poly crystal[4] as shown in the schematic figure (Fig.1). In addition, memory devices also have almost the same transistor structure. Shrinking active Si areas in transistors of flash memory embedded in surrounding STI oxide is similar structure as tall Si fin in FinFET structures. Doping with ion implantation causes narrow active Si areas amorphous, and regrowth to the active Si top is also becoming difficult. Doping without Si amorphization is a challenge for further scaling of transistors both in logic devices and memory devices. This paper reports high dose doping by using implantation to heated Si substrates. Crystalline quality, depth profiles and resistance of As⁺, P⁺ and BF₂⁺ implanted Si at elevated temperatures have been investigated. It will be shown that high dose doping without amorphization, and also low resistance of implanted regions after annealing can be successfully embodied.