DocumentCode
1878210
Title
Parallel regeneration of interconnections in VLSI & ULSI circuits
Author
Nekili, M. ; Savaria, Yvon
Author_Institution
Ecole Polytechnique of Montreal
fYear
1993
fDate
3-6 May 1993
Firstpage
2023
Lastpage
2026
Keywords
Delay effects; Integrated circuit interconnections; Integrated circuit technology; Inverters; Logic; Propagation delay; Ultra large scale integration; Very large scale integration; Voltage; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
IEEE
Print_ISBN
0-7803-1281-3
Type
conf
Filename
693076
Link To Document