• DocumentCode
    1878323
  • Title

    Efficient sparse matrix multiple-vector multiplication using a bitmapped format

  • Author

    Kannan, Ravindran

  • Author_Institution
    Sch. of Math., Univ. of Manchester, Manchester, UK
  • fYear
    2013
  • fDate
    18-21 Dec. 2013
  • Firstpage
    286
  • Lastpage
    294
  • Abstract
    The problem of obtaining high computational throughput from sparse matrix multiple-vector multiplication routines is considered. Current sparse matrix formats and algorithms have high bandwidth requirements and poor reuse of cache and register loaded entries, which restrict their performance. We propose the mapped blocked row format: a bitmapped sparse matrix format that stores entries as blocks without a fill overhead, thereby offering blocking without additional storage and bandwidth overheads. An efficient algorithm decodes bitmaps using de Bruijn sequences and minimizes the number of conditionals evaluated. Performance is compared with that of popular formats, including vendor implementations of sparse BLAS. Our sparse matrix multiple-vector multiplication algorithm achieves high throughput on all platforms and is implemented using platform neutral optimizations.
  • Keywords
    cache storage; digital arithmetic; matrix multiplication; sparse matrices; vectors; bandwidth overhead; bandwidth requirement; bitmap decoding; bitmapped format; bitmapped sparse matrix format; cache reuse; computational throughput; conditionals number minimization; de Bruijn sequences; fill overhead; mapped blocked row format; platform neutral optimization; register loaded entries; sparse BLAS; sparse matrix multiple-vector multiplication algorithm; Arrays; Bandwidth; Kernel; Optimization; Registers; Sparse matrices; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing (HiPC), 2013 20th International Conference on
  • Conference_Location
    Bangalore
  • Type

    conf

  • DOI
    10.1109/HiPC.2013.6799135
  • Filename
    6799135