A study of new type CMOS inverter with Gated-IIP load and TFET driver for 22nm technology node

Author

Hsueh-Liang Huang ; Jyi-Tsong Lin ; Chen-Chi Tsai ; Kuan-Yu Chen ; You-Ren Lu ; Shih-Wen Hsu ; Po-Hsieh Lin

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2013

fDate

6-7 June 2013

Firstpage

109

Lastpage

113

Abstract

This paper presents a new CMOS inverter (CGTFET), which is composed of a Gated control IIP for load transistor (Gated-IIP) and a tunneling field effect transistor (TFET) for driven transistor. Based on the measurement data of Gated-IIP and TFET devices published, we have for the first time drawn the load lines and the quiescent point line (Q line) of the new designed CGTFET compared with the conventional CTFET to verify its feasibility. Additionally, due to our unique structure has simple fabrication process and the output node is shared by the load and the driver, the integration density of our structure can be reduced dramatically. The area benefit thus more than 32.6% has been achieved compared with the conventional CTFET layout. Further, we use Ge Source to further improve NTFET (Q1) driven ability and the performance of the CGTFET.

Keywords

CMOS integrated circuits; field effect transistors; germanium; invertors; CGTFET; CMOS inverter; Ge; NTFET; TFET driver; gated-IIP load; integration density; load transistor; quiescent point line; size 22 nm; tunneling field effect transistor; CMOS integrated circuits; Conferences; Inverters; Junctions; Logic gates; Power demand; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology (IWJT), 2013 13th International Workshop on

Conference_Location

Kyoto

Print_ISBN

978-1-4799-0578-2

Type

conf

DOI

10.1109/IWJT.2013.6644518

Filename

6644518