Title :
A low-cost media-processor based real-time MPEG-4 video decoder
Author :
Jin-Hau Kuo ; Ja-Ling Wu ; Jim Shiu ; Kan-Li Huang
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper by implementing a realistic MPEG-4 core profile decoder over the TriMedia/spl trade/ DSP chip, we investigate a series of important issues related to the use of a media-processor to satisfy multimedia compression and processing requirements. The realistic MPEG-4 decoder optimized implementation by this DSP chip can support resolutions up to 4 CIF (720/spl times/576) at 30 fps. The issues we investigated include the overview of characteristics of media-processor architecture, the speedup of the MPEG-4 decoder based on the TriMedia/spl trade/ DSP chip, multimedia co-processor or hardware accelerator based approaches, Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) programming technique and the media-processor based solution for set-top box applications.
Keywords :
code standards; coprocessors; decoding; digital signal processing chips; image resolution; multimedia computing; parallel processing; real-time systems; video codecs; video coding; 4CIF resolution; MPEG-4 core profile decoder; SIMD programming; Single Instruction Multiple Data programming; TriMedia DSP chip; VLIW programming; Very Long Instruction Word programming; hardware accelerator; media-processor architecture; multimedia co-processor; multimedia compression; realistic MPEG-4 decoder; set-top box applications; speedup; video decoder; Acceleration; Decoding; Digital TV; Digital signal processing chips; Discrete cosine transforms; MPEG 4 Standard; Motion compensation; Multimedia communication; VLIW; Video compression;
Conference_Titel :
Consumer Electronics, 2002. ICCE. 2002 Digest of Technical Papers. International Conference on
Conference_Location :
Los Angeles, CA, USA
Print_ISBN :
0-7803-7300-6
DOI :
10.1109/ICCE.2002.1014026
