Title :
Gate array placement based on mincut partitioning with path delay constraints
Author :
Wakabayashi, Shin´ichi ; Kusumoto, Hiroyuki ; Mishima, Hidetoshi ; Koide, Tetsushi ; Yoshida, Norihiro
Author_Institution :
Hiroshima University
Keywords :
Capacitance; Circuit simulation; Delay; Integrated circuit interconnections; Iterative algorithms; Pins; Simulated annealing; Timing; Very large scale integration; Wire;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
IEEE
Print_ISBN :
0-7803-1281-3
