Modified architecture for real-time face detection using FPGA

Author

Das, S. ; Jariwala, A. ; Engineer, P.

Author_Institution

Electron. Eng. Dept., Sardar Vallabhbhai Nat. Inst. of Technol., Surat, India

fYear

2012

fDate

6-8 Dec. 2012

Firstpage

1

Lastpage

5

Abstract

In this paper, we introduce modified hardware architecture with key features of lessening the resource usage of the FPGA and elevating the face detection frame rate. The system is based on well-known Viola Jones Framework which consists of AdaBoost algorithm integrated with Haar features. We also enlist the modification in hardware design techniques to achieve more parallel processing and higher detection speed of the system. The system implemented on Xilinx Virtex-5 FPGA development board outputs a high face detection rate (91.3%) at 60 frame/second for a VGA (640 × 480) video source. The power consumption of the implementation is 2.1 W.

Keywords

Haar transforms; face recognition; field programmable gate arrays; learning (artificial intelligence); parallel architectures; resource allocation; video signal processing; AdaBoost algorithm; FPGA resource usage; Haar features; VGA video source; Viola Jones framework; Xilinx Virtex-5 FPGA development board; detection speed; hardware design techniques; high face detection rate; modified hardware architecture; parallel processing; power consumption; real-time face detection frame rate; AdaBoost; FPGA; Face detection; Haar classifier; real-time system;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering (NUiCONE), 2012 Nirma University International Conference on

Conference_Location

Ahmedabad

Print_ISBN

978-1-4673-1720-7

Type

conf

DOI

10.1109/NUICONE.2012.6493235

Filename

6493235