مرکز منطقه ای اطلاع رساني علوم و فناوري - Reducing the physical design cycle by means of topological placement with hard timing restraints

DocumentCode :

1878610

Title :

Reducing the physical design cycle by means of topological placement with hard timing restraints

Author :

Freier, B.E.

Author_Institution :

GMD-SET

fYear :

1993

fDate :

3-6 May 1993

Firstpage :

2063

Lastpage :

2066

Keywords :

Algorithm design and analysis; Circuits; Clocks; Delay effects; Pins; Relays; Sorting; Surface topography; Time to market; Timing;

fLanguage :

English

Publisher :

ieee

Conference_Titel :

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location :

IEEE

Print_ISBN :

0-7803-1281-3

Type :

conf

Filename :

693086

Link To Document :