Issues in the implementation of the i486 cache and bus

To meet its performance goal of executing most instructions in a single clock, the i486 microprocessor uses a cache memory that is integrated on the silicon die as the processor. The integrated cache is capable of performing one memory read or write each clock cycle. The size and organization of the cache were selected based on available silicon area and on the results of trace-driven simulation. An external bus was devised featuring burst data transfers to quickly fill cache lines and provisions to ensure cache coherency