Three-phase digital PLL for synchronizing on three-phase/switch/level boost rectifier by DSP

This article presents the study and implementation of a three-phase three-level preregulator rectifier with digital control using a DSP. A synchronizing circuit (DPLL - digital phase locked loop) tracks continuously the fundamental frequency of the system voltage. This digital PLL circuit determines the frequency and phase angle of the fundamental positive-sequence component of the measured signals to the phase voltages. The converter structure has a common capacitive center point that allows the three-level operation and a low blocking-voltage stress on the power switches (half of delink voltage). The reduction of blocking voltage allows the use of low cost and low losses power devices, increasing the efficiency and the power density with reduced production cost. The control technique used aims to obtain power factor correction (PFC), regulated and balanced output voltages. With the advance of DSP controllers, digital control is increasingly used in power converts systems and offers a number of advantages like more flexibility in modification code and less sensitive to noise. However, sampling time delay, resolution of A/D converter, word length of DSP and instructions cycle time are disadvantages over analog control. Nowadays, control optimized DSP´s deliver high performance, great code efficiency and optimal peripheral integration for the digital control with high level on-chip integration to deliver system cost reduction, and powerful computational abilities that enable software innovation then reducing disadvantages of a digital control. The DSP used is the ADMC401 from analog devices.