Design-space exploration between FPGA and ASIF

Application-Specific Inflexible FPGA (ASIF) [1] is an FPGA reduced and optimized for a known set of application circuits. An ASIF achieves considerable area gain compared to an FPGA. However, this area gain is achieved at the expense of reduced routing flexibility, thus making the architecture highly irregular. As a consequence, the irregular ASIF architecture cannot be fabricated through the tile based abutment process, besides having other negative implications. This paper explores the design-space between FPGA and ASIF to generate reconfigurable Regular-ASIF architectures with maneuverable regularity and flexibility. Our preliminary experiments have shown some promising results; on average ASIF architecture is 5.6×, whereas Regular-ASIF is 1.02× to 2.1× smaller than a mesh-based unidirectional FPGA architecture.