Sram-Based FPGA proposal for dynamic power management on sensor node

Technologies like Sram-Based FPGA appear with features to be explored as construction of low-power circuits. In this project we built a low-power circuit applying the implementation of a technique to minimize the clocks domains of the circuit reducing an amount of 87% of dynamic power with respect to the same architecture built with a clock domain for each module. The architecture built has all the necessary features to integrate, synchronize and to perform communication according to the application. The impact of dynamic power consumption in the architecture built on Sram-Based FPGA is evaluated. Also a balanced operation mode among performance, reliability in the communication and power consumption for sensor nodes on FPGA is achieved. The full operation mode of the architecture described is proposed and analyzed in an eASIC Nextreme-2 technology.