Integrated switched-capacitor voltage doubler with clock transition periods boosting and transfer blocking techniques

In this paper, a CMOS switched-capacitor voltage doubler is proposed. It employs the techniques of clock synchronization and charge transfer blocking to minimize the reversion loss. The clock transition period detection and boosting circuit modules allow continuous charge action to the output node, which significantly improves operation performances. The proposed voltage doubler was designed using IBM 180 nm CMOS process, with a 1.2 V supply voltage. Under no-load condition, it achieves 99.92% of ideal voltage level with 8 mV voltage ripple, while consuming only 9.6 ¿W of quiescent power. With a load ranging from 20 k¿ to 200 k¿, the up-conversion ratio performs 45% better than the prior arts.