Fault modeling for MOS digital circuits using current limited switch

Author

Ruan, G. ; Vlach, J. ; Barby, J.

Author_Institution

Waterloo Univ., Ont., Canada

fYear

1988

fDate

7-9 Jun 1988

Firstpage

681

Abstract

A fault model for MOS digital circuits is presented. Only two types of faults, and node-short and line-open, are needed to model hard physical failures occurring in MOS integrated circuits. Complicated failures are modeled as multiple-faults consisting of a number of faults of these two types. The model is isomorphic to realistic MOS circuits and can be used in simulating NMOS, CMOS, CVSL, DSLL, and dynamic MOS circuits. Three examples have been discussed and the results compared with outputs of circuit-level simulators

Keywords

CMOS integrated circuits; VLSI; circuit reliability; digital simulation; failure analysis; field effect integrated circuits; integrated logic circuits; logic testing; CMOS; CVSL; DSLL; MOS digital circuits; MOS integrated circuits; NMOS; cascode voltage switch logic; current limited switch; differential split level logic; dynamic MOS circuits; fault model; fault modeling; hard physical failures; line-open; multiple-faults; node-short; outputs of circuit-level simulators; Attenuators; Circuit faults; Circuit simulation; Connectors; Digital circuits; Integrated circuit modeling; Logic; Semiconductor device modeling; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo

Type

conf

DOI

10.1109/ISCAS.1988.15017

Filename

15017