Parallel VLSI equalizer architectures for multi-Gbps satellite communications

This paper provides an overview of a new VLSI architecture for implementing a frequency domain LMS complex equalizer. The architecture incorporates a simple sub-convolution method, digital vector processing, specialized FFT-IFFT hardware architectures, and the DFT-IDFT overlap-and-save filter method. A key property of the new architecture is that the equalizer tap length may be chosen completely independently of the FFT-IFFT lengths and input data block lengths. Theoretically unlimited tap lengths are possible with short FFT-IFFT pairs. It is demonstrated that the new parallel architecture is very well suited for processing multi-Gbps digital communication data rates with relatively low speed CMOS hardware. The presented VLSI equalizer architecture processes complex demodulated symbols at 1/4 the symbol rate. The parallel equalizer, operating on one sample per symbol, has 32 coefficients, is decision directed and processes data modulated with QPSK and 16QAM. The equalizer is integrated into the 2.4 Gbps all-digital wireless parallel demodulator ASIC. The receiver is currently being developed by JPL/CalTech and NASA´s Goddard Space Flight Center. This parallel all-digital receiver designed for satellite communications operates at 1/16 the analog-to-digital sample rate. Finally, a complexity comparison between this equalizer architecture and the traditional frequency domain fast LMS equalizer is given