VLSI implementation of Mallat´s fast discrete wavelet transform algorithm with reduced complexity

Author

Guo, Yuanbin ; Zhang, Hongzhong ; Wang, Xuguang ; Cavallaro, Joseph R.

Author_Institution

Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA

Volume

1

fYear

2001

fDate

2001

Firstpage

320

Abstract

This paper proposes a novel VLSI architecture to compute the DWT (discrete wavelet transform) coefficients using Mallat´s algorithm with reduced complexity. We studied the commonality embedded in the mirror low-pass and high-pass filters of the algorithm and use a PLA as an address generator (PAG) to load the data for cascaded FIR computation. By using an embedded downsampling process in the control signal design, we reduced the complexity by saving storage and computation. The prototyping design is implemented and fabricated using the AMI 1.5 micron CMOS process through the MOSIS service

Keywords

CMOS digital integrated circuits; FIR filters; VLSI; application specific integrated circuits; discrete wavelet transforms; high-pass filters; integrated circuit design; low-pass filters; programmable logic arrays; signal sampling; 1.5 micron; ASIC; CMOS process; DWT; FIR filtering; MOSIS prototyping service; Mallat algorithm; PLA; VLSI implementation; address generator; discrete wavelet transform; embedded downsampling process; high-pass filter; low-pass filter; mirror filters; time-frequency analysis; Computer architecture; Discrete wavelet transforms; Embedded computing; Finite impulse response filter; Low pass filters; Mirrors; Process control; Programmable logic arrays; Signal design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 2001. GLOBECOM '01. IEEE

Conference_Location

San Antonio, TX

Print_ISBN

0-7803-7206-9

Type

conf

DOI

10.1109/GLOCOM.2001.965131

Filename

965131