Better-Than-DMR Techniques for Yield Improvement

Author

Sanae, Shunichi ; Hara-Azumi, Yuko ; Yamashita, Shigeru ; Nakashima, Yasuhiko

Author_Institution

Nara Inst. of Sci. & Technol., Nara, Japan

fYear

2014

fDate

11-13 May 2014

Firstpage

34

Lastpage

34

Abstract

In this work, we first study LUT optimization in PPCs for increasing their area-efficiency for yield improvement. We focus on the fact that although 2²ⁿ configurations are available for an-input LUT, such full programmability is not needed, i.e., one configuration is enough for bypassing one specific fault. Then, we optimize away too rich programmability of LUTs exploiting application features in order to reduce the area cost without degrading the fault bypassability from the original PPC.

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit reliability; redundancy; CMOS technology; LUT optimization; PPCs; area cost reduction; area-efficiency; better-than-DMR techniques; dual-modular redundancy; yield improvement; Benchmark testing; Circuit faults; Logic gates; Optimization; Table lookup; Transistors; Wires; Logic Synthesis; Multiple Functional Redundancy; Partially-Programmable Circuit; Yield Improvement;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines (FCCM), 2014 IEEE 22nd Annual International Symposium on

Conference_Location

Boston, MA

Print_ISBN

978-1-4799-5110-9

Type

conf

DOI

10.1109/FCCM.2014.21

Filename

6861583