Title :
A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture
Author :
Tian Xiang ; Lei Zhao ; Xi Jin ; Tianqi Wang ; Shaoping Chu ; Cong Ma ; Shubin Liu ; Qi An ; Xue Ben
Author_Institution :
State Key Lab. of Particle Detection & Electron., Univ. of Sci. & Technol. of China, Hefei, China
Abstract :
The time-to-digital converter(TDC) aims to mark an accurate timestamp at the time of input signal comes. The Multi-phase Clock sampling method is an usual way to map the TDC into an FPGA. Traditionally, this method provides a medium accuracy and low resources occupation. In this paper, we present a new architecture of TDC base on the 2-ISERDES in the SelectIO, rather than utilizing the Slice resources by the old way. The ISERDESes based TDC is equivalent to a 8 equidistant phase-shifted clocks TDC, with maximum clock frequency 900MHz. The least significant bit(LSB) is 139ps, which is 445% better than traditional architecture.
Keywords :
clocks; field programmable gate arrays; input-output programs; phase shifters; resource allocation; time-digital conversion; 2-ISERDES architecture; FPGA; SelectIO; Slice resource utilization; frequency 900 MHz; least significant bit; low resources occupation; maximum clock frequency; multiphase clock sampling method; multiphase clock time-to-digital convertor; phase-shifted clocks TDC; timestamp; Clocks; Computer architecture; Delays; Educational institutions; Field programmable gate arrays; Signal resolution; Synchronization; FPGA TDC ISERDES;
Conference_Titel :
Field-Programmable Custom Computing Machines (FCCM), 2014 IEEE 22nd Annual International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
978-1-4799-5110-9
DOI :
10.1109/FCCM.2014.22
