Multi-output synchronously-rectified forward converter with load transient considered

In this paper, an FPGA-counter-based scheme is presented herein and applied to a forward converter with single isolation stage and multiple outputs having synchronous rectification (SR). With only the required comparators and without any analog-to-digital converter (ADC), the information on feedback output voltage is entirely obtained according to a counter. Therefore, the proposed control topology for an SR forward converter can improve the load transient response and the cross regulation. Besides, to further upgrade the load transient response, the proposed nonlinear control technique is applied. In this paper, the proposed control scheme is described and some experimental results are provided to verify its effectiveness.