Junction evaluation by time dependent degradation due to high constant voltage stressing [DRAMs]

Author

Mitsuhashi, Junichi ; Komori, Junko ; Eimori, Takahisa ; Koyama, Hiroshi

Author_Institution

Mitsubishi Electric Corp., Hyogo, Japan

fYear

1993

fDate

22-25 Mar 1993

Firstpage

121

Lastpage

124

Abstract

Wafer-level time dependent junction degradation (TDJD) is investigated as a technique for evaluating junction reliability. The TDJD phenomenon due to latent defects is revealed by high constant voltage stressing, in the same way that the TDDB test determines the long-term reliability of the junction. Latent defects enhance the junction degradation due to TDJD. Electrons trapped at the perimeter of a junction degrade junction characteristics. Although the perimeter of a junction is composed with local oxidation of silicon (LOCOS) and/or gate edge, the gate edge is found to be more significant for the TDJD characteristics

Keywords

DRAM chips; MOS integrated circuits; VLSI; circuit reliability; integrated circuit technology; integrated circuit testing; LOCOS; TDJD phenomenon; constant voltage stressing; gate edge; junction reliability; latent defects; local oxidation of silicon; long-term reliability; time dependent degradation; Aging; Breakdown voltage; Degradation; Electric breakdown; Leakage current; P-n junctions; Random access memory; Stress; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on

Conference_Location

Sitges

Print_ISBN

0-7803-0857-3

Type

conf

DOI

10.1109/ICMTS.1993.292883

Filename

292883