Designing and implementing OFDM communications for Advanced Multifunction UAV payloads using FPGAs

Unmanned Aerospace Vehicles (UAVs) have become a ubiquitous platform for a wide variety of aerospace missions. Such missions cover a broad range from Search and Rescue to providing real-time Situational Awareness (SA) of a local area. Ultimately UAV missions that require real-time mission information are limited by the amount of on-board signal processing for the sensors, onboard sensor processing algorithm size, type and complexity as well as the capability to move mission information in real-time to Users via on-board communication links. Advanced Multifunction UAV payloads support not only sensor processing, but additional on-board Digital Signal Processing (DSP) and high bandwidth air-to-air and air-to-ground communications. Such a design approach pushes both the signal processing load and the communications bandwidth challenges into the UAV payload. This results in real-time capabilities that increase the performance envelope of UAVs allowing functionality beyond low bandwidth sensor processing at the cost of increased payload complexity. This paper discusses the design and implementation of such Advanced Multifunction UAV payloads using Field Programmable Gate Arrays (FPGAs). Specifically, this article discusses FPGA based UAV payload design to support sensor processing, maximizing on-board DSP algorithm processing, and high bandwidth Orthogonal Frequency Division Multiplexing (OFDM) based communications. Furthermore, this paper focuses on the use of Cascaded Frequency-Domain (CFD) filtering techniques and dedicated subcarrier tones to solve the challenging task of OFDM frequency acquisition and tracking in high Doppler and Doppler rate environments such as UAV communications. Design data for frequency acquisition and tracking using CFD filtering is provided in the paper, as well as reference circuits for synchronization of OFDM communications. Finally, an example OFDM payload design based on Xilinx Virtex-6 FPGAs is provided to illustrate the concepts discus- ed in the paper.