Title :
Modeling of real defect outlines for defect size distribution and yield prediction
Author :
Hess, Christopher ; Ströle, Albrecht
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
For efficient yield, prediction defects are usually modeled by circular disks or squares. A more accurate model is presented. It considers the real outline of physical defects. To utilize this model, only the maximum and the minimum extension of detected defects must be determined. That can be done easily using a checkerboard test structure including a defect localization procedure. The accuracy of the predicted number of defects can be substantially enhanced by modeling real defect outlines with this elliptical model. If the elliptical model of the defect outlines is applied, the defect size distribution implicitly contains information about the physical defect outlines. Hence, for yield prediction the inspection of defect outlines can be omitted
Keywords :
VLSI; integrated circuit testing; monolithic integrated circuits; semiconductor process modelling; checkerboard test structure; defect localization procedure; defect outlines; defect size distribution; elliptical model; maximum extension; minimum extension; yield prediction; Circuit faults; Circuit testing; Data mining; Distributed computing; Fault tolerance; Frequency; Predictive models; Semiconductor device measurement; Shape; Structural discs;
Conference_Titel :
Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on
Conference_Location :
Sitges
Print_ISBN :
0-7803-0857-3
DOI :
10.1109/ICMTS.1993.292890